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irf3546 60a dual integrated pow er b lock www.irf.com | ? 2013 international rectifier may 2 9 , 2013 | final 1 features ? peak efficiency up to 94 % at 1.2v ? two pairs of control and sync hronous mosfets in a single pqfn package ? proprie tary package minimizes package parasitic and simplifies pcb layout ? input v oltage (vin) range of 4.5v to 2 1 v ? output current capability of 30a/phase ? ultra - low rg mosfet technology minimizes switching losses for optimized high frequency performance ? synchronous mosfet with monolithic integrated schottky diode reduces dead - time and diode reverse recovery losses ? efficient dual side cooling ? sma ll 6mm x 8 mm x 0.9mm pqfn package ? lead - free rohs compliant package applications ? high frequency, low profile dc - dc converters ? voltage regulators for cpus, gpus, and ddr memory arrays description the irf3546 dual int egrated pow er block co - packages two pairs of high performance control and synchronous mosfets and is ideal for use in high - density two - phase synchronous buck converters . it is optimized internally for pcb layout, heat transfer and package inductance . coupled with the latest generation of ir mosfet technology, the irf3546 provides higher efficiency at low output voltages required by cutting edge cpu , gpu and ddr memory designs. high switching frequency enables high performance transient response, allowing miniaturization of output inductors, as well as input and output capacitors while maintaining industry leading efficiency. integrating two phases in one package while still providing superior efficiency and thermal performance , the irf3546 enables smallest size solutions . the irf3546 uses ir s latest generation of low voltage mosfet technology characterized by ultra - low gate resistance (rg , < 0.5 ) and charge that result in minimized switching losses. the synchronous mosfet optimizes conduction losses and features a monolithic integrated schot tky to significantly reduce dead - time and diode conduction and reverse recovery losses. the irf3546 is optimized specifically for cpu core power delivery in 12v input applications like servers, certain notebooks, gpu and ddr memory designs. ordering in formation base part number package type standard pack orderable part number form quantity irf 3546 pqfn 6 mm x 8 mm tape and reel 3 000 irf 3546 m trpbf
irf3546 60a dual integrated pow er b lock www.irf.com | ? 2013 international rectifier may 2 9 , 2013 | final 2 pinout diagram figure 1: irf3546 top view functional block dia gram figure 2 : block diagram vin 1 21 22 23 24 25 26 27 28 40 41 15 16 17 vin 1 vin 1 vin 2 vin 2 vin 2 sw 2 sw 2 sw 2 sw 2 sw 2 sw 2 sw 2 sw 2 19 20 pgnd pgnd 18 gatel 2 9 gateh 2 38 39 pgnd pgnd 37 gatel 1 7 gateh 1 1 29 30 31 32 33 34 35 36 sw 1 sw 1 sw 1 sw 1 sw 1 sw 1 sw 1 sw 1 8 42 pgnd irf 3546 pgnd q 1 q 2 q 3 q 4
irf3546 60a dual integrated pow er b lock www.irf.com | ? 2013 international rectifier may 2 9 , 2013 | final 3 typ ical application figure 3 : high density two phase voltage regulator sw 1 irf 3546 vin 1 pgnd vout 1 c 1 10 uf x 2 l 1 150 nh c 3 22 uf x 5 1 , 40 , 41 38 , 39 29 - 36 c 2 0 . 1 uf gatel 1 37 sw 2 vin 2 pgnd vout 2 c 4 10 uf x 2 l 2 150 nh c 6 22 uf x 5 15 - 17 19 , 20 21 - 28 c 5 0 . 1 uf gatel 2 18 gateh 2 9 gateh 1 7 pgnd 8 , 42 q 1 q 2 q 3 q 4
irf3546 60a dual integrated pow er b lock www.irf.com | ? 2013 international rectifier may 2 9 , 2013 | final 4 pin descriptions pin # pin name pin description 1 , 40, 41 vin 1 high current input supply pads. connected to drains of q1 . recommend ed operating range is 4.5v to 21 v. connect at l east two 10uf 1206 ceramic capacitors and a 0.1uf 0402 ceramic capacitor. place the capacitors as close as possible to vin 1 pins ( 40 and 41) and pgnd pins ( 38 and 39 ). the 0.1uf 0402 capacitor should be on the same s ide of the pcb as the irf3546 . 2 - 6, 10 - 14 no connect no connects. these pins can be connected to the vin planes to reduce pcb trace resistances. 7 gateh 1 gate connection of the channel 1 control mosfet q1 . 8, 19, 20, 38, 39, 42 pgnd high current power ground. connected to sources of q2 and q4 . note all pads are internally connected in the package. provide low resistance connections to the ground plane and respective output capacitors. 9 gateh2 gate connection of the channel 2 control mosfet q3 . 15 - 17 vin 2 high current input supply pads. con nected to drains of q3. recommend ed operating range is 4.5v to 21 v. connect at least two 10uf 1206 ceramic capacitors and a 0.1uf 0402 ceramic capacitor. place the capacitors as close as possible to vin 2 pins (16 and 17) and pgnd pins ( 19 and 20 ). the 0.1u f 0402 capacitor should be on the same s ide of the pcb as the irf3546 . 18 gatel2 gate connection of the channel 2 synchronous mosfet q4 . 21 - 28 sw2 high current switch node output for channel 2. connected to source of q3 and drain of q4. 29 - 36 sw1 high current switch node output for channel 1. connected to source of q1 and drain of q2. 37 gatel1 gate connection of the channel 1 synchronous mosfet q2 .
irf3546 60a dual integrated pow er b lock www.irf.com | ? 2013 international rectifier may 2 9 , 2013 | final 5 absolute maximum rat ings stresses beyond those listed under absolute maximum ratings may cause pe rmanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. parameter q1 and q3 max. q2 and q 4 max. units v ds drain - to - source voltage 25 v v gs gate - to - source voltage 20 v i d @t c = 25 c continuous drain current, v gs @ 10v 16 20 a i d @t c = 70 c continuous drain current, v gs @ 10v 13 16 a i dm pulse drain current 130 160 a e as single pulse aval anche energy 50 note 1 200 note 2 mj thermal information thermal resistance, junction to top ( jc _top ) 11.3 c/w thermal resistance, junction to pcb ( pin 28 ) ( j b ) 1.6 c/w thermal resistance ( ja ) note 3 18.4 c/w maximum operating junction temperature - 40c to 150c maximum storage temperature range - 5 5c to 150c msl rating msl3 reflow temperature 260c notes 1. t j =25c, l =100uh, r g =50 , i as =32a. 2. t j =25c, l =100uh, r g =50 , i as =63a. 3. thermal resistance ( ja ) is measured with the component mounted on a high effective thermal cond uctivity test board in free air. refer to international rectifier application note an - 994 for details.
irf3546 60a dual integrated pow er b lock www.irf.com | ? 2013 international rectifier may 2 9 , 2013 | final 6 electrical specifica tions the electrical characteristics involve the spread of values guaranteed within the recommended operating conditions. typical values represent the median values, which are related to 25c. electrical character istics parameter symbol conditions min typ max unit efficiency pow er block per - channel peak efficiency note 2 9 4 % note 3 9 3 % control mosfet s (q1 and q3) drain - to - source on - resistance r ds(on)_ 4. 5v_25c v gs = 4. 5v, i d = 13a , t j =25c 4. 1 4.8 m? drain - to - source on - resistance r ds(on)_10 v_25c v gs = 10v , i d = 27 a , t j =25c 3.2 3. 9 m? drain - to - source br eakdown voltage bv dss v gs =0v, i d = 250u a , t j =25c 25 v breakdown voltage temperature coefficient ? bv dss / ?t j t j = 25 c - 125c , note 1 0.02 v/c drain - to - source leakage current i dss v ds =20v, v gs =0v, t j =25c 1 ? a gate - to - source forward leakage curr ent i gss v gs = 16 v 100 na gate - to - source reverse leakage current i gss v gs = - 16 v - 100 na gate threshold voltage v gs(th) v ds = v gs , i d =35ua 1.1 1.6 2.1 v gate threshold voltage coefficient ? v gs(th) v ds = v gs , i d =35ua - 5.7 mv/ c total gate charge q g v ds = 13v, v gs =4.5 v , i d =13a , note 1 9.7 15 nc pre - vth gate - to - source charge q gs1 v ds = 13v, v gs =4.5 v , i d =13a 2.3 nc post - vth gate - to - source charge q gs2 v ds = 13v, v gs =4.5 v , i d =13a 1.8 nc gate - to - drain charge q gd v ds = 13v, v gs =4.5 v , i d =13a 3 . 1 nc gate charge overdrive q godr v ds = 13v, v gs =4.5 v , i d =13a 2.9 nc switch charge ( q gs2 +q gd ) q sw v ds = 13v, v gs =4.5 v , i d =13a 4. 9 nc output charge q oss v ds = 16 v, v gs = 0v 13 nc gate resistance r g 0.6 ? turn - on delay time t d(on) v d d = 13v, v gs =4.5 v , i d =13a , r g =1.8 ? 7.5 ns rise time t r v d d = 13v, v gs =4.5 v , i d =13a , r g =1.8 ? 12 n s turn - off delay time t d v d d = 13v, v gs =4.5 v , i d =13a , r g =1.8 ? 6.7 n s fall time t f v d d = 13v, v gs =4.5 v , i d =13a , r g =1.8 ? 4.2 n s input capacitance c iss v gs = 0 v, v d s = 13v , f =1 .0mhz 1310 pf output capacitance c oss v gs = 0 v, v d s = 13v , f =1 .0mhz 380 pf reverse transfer capacitance c rss v gs = 0 v, v d s = 13v , f =1 .0mhz 90 pf diode forward voltage v sd v gs =0v, i s =13a, t j =25 c 0.72 0.80 0.88 v reverse recovery time t rr t j =25c, i f =30a, v dd =13v, di/dt=200a/us, note 1 15 23 n s reverse recovery charge q rr t j =25c, i f =30a, v dd =13v, di/dt=200a/us, note 1 10 15 nc
irf3546 60a dual integrated pow er b lock www.irf.com | ? 2013 international rectifier may 2 9 , 2013 | final 7 parameter symbol conditions min typ max unit synchronous mosfet s (q2 and q4) drain - to - source on - resistanc e r ds(on)_4.5v_25c v gs =4.5v, i d =16a, t j =25c 1.8 2.2 m? drain - to - source on - resistance r ds(on)_10v_25c v gs =10v, i d =30a, t j =25c 1.35 1.8 m? drain - to - source breakdown voltage bv dss v gs =0v, i d =1ma , t j =25c 25 v breakdown voltage temperature coefficient ? bv dss / ?t j t j =25c - 125c , note 1 0.02 v/c drain - to - source leakage current i dss v ds =20v, v gs =0v, t j =25c 250 ua gate - to - source forward leakage current i gss v gs =16v 100 na gate - to - source reverse leakage current i gss v gs = - 16v - 100 na gate threshold voltage v gs(th) v ds = v gs , i d =100 ua 1.1 1.6 2.1 v gate threshold voltage coefficient ? v gs(th) v ds = v gs , i d =1m a - 5.4 mv/ c total gate charge q g v ds = 13v, v gs ,=4.5v, i d =30a, note 1 22 33 nc pre - vth gate - to - source charge q gs1 v ds = 13v, v gs =4.5v, i d =30a 5.1 nc post - vth gate - to - source charge q gs2 v ds = 13v, v gs =4.5v, i d =30a 3.1 nc gate - to - drain charge q gd v ds = 13v, v gs =4.5v, i d =30a 6.0 nc gate charge overdrive q godr v ds = 13v, v gs =4.5v, i d =30a 6.7 nc switch charge ( q gs2 +q gd ) q sw v ds = 13v, v gs =4.5v, i d =30a 9.1 nc output charge q oss v ds = 16v, v gs =0v 23 nc gate resistance r g 0.4 ? turn - on delay time t d(on) v dd = 13v, v gs =4.5v, i d =16a, r g =1.3 ? 13 ns rise time t r v dd = 13v, v gs =4.5v, i d =16a, r g =1.3 ? 15 ns turn - off delay time t d v dd = 13v, v gs =4.5v, i d =16a, r g =1.3 ? 16 ns fall time t f v dd = 13v, v gs =4.5v, i d =16a, r g =1.3 ? 6.6 ns input capacitance c iss v gs = 0v, v ds =13v, f=1.0mhz 2880 pf output capacitance c oss v gs = 0v, v ds =13v, f=1.0mhz 950 pf reverse transfer capacitance c rss v gs = 0v, v ds =13v, f=1.0mhz 180 pf diode forward voltage v sd v gs =0v, i s =30a, t j =25 c 0.63 0.70 0.77 v diode forward voltage v sd v gs =0v, i s =13a, t j =25c 0.54 0.60 0.66 v reverse recovery time t rr t j =25c, i f =30a, v dd =13v, di/dt=200a/us, note 1 23 35 ns reverse recovery charge q rr t j =25c, i f =30a, v dd =13v, di/dt=200a/us, note 1 30 45 nc notes 1. guaranteed by design but not tested in production 2. v in =12v, v out =1.2v, ? sw = 300khz, l=210nh (0.2 9 m), vcc=6.8v, c in =47uf x 4, c out =470uf x3, 400lfm airflow, no heat sink, 25c ambient temperature, and 8 - layer pcb of 3.7 (l) x 2.6 ( w). pwm controller loss and inductor loss are not included. 3. v in =12v, v out =1.2v, ? sw = 400khz, l=150nh (0.29m), vcc=6.8 v, c in =47uf x 4, c out =470uf x3, no airflow, no heat sink, 25c ambient temperature, and 8 - layer pcb of 3.7 (l) x 2.6 (w). pwm con troller loss and inductor loss are not included.
irf3546 60a dual integrated pow er b lock www.irf.com | ? 2013 international rectifier may 2 9 , 2013 | final 8 typical operating ch aracteristics t a = 25c , no heat sink, no air flow, 8 - layer pcb board of 3.7 (l) x 2.6 (w), unless specified otherwise. figure 4: q1 & q3 typical output characteristics figure 5 : q1 & q3 typical output characteristics @150 o c figure 6 : q1 and q3 typical transfer characteristics figure 7 : q2 & q4 typical output characteristics figure 8 : q2 & q4 typical output characte ristics @150 o c figure 9 : q 2 and q 4 typical transfer characteristics 0.1 1 10 100 1000 0.1 1 10 100 v ds , drain-to-source voltage (v) i d , drain-to-source current (a) vgs top 10v 5v 4.5v 3.5v 3.3v 3v 2.8v bottom 2.5v 0.1 1 10 100 1000 0.1 1 10 100 v ds , drain-to-source voltage (v) i d , drain-to-source current (a) vgs top 10v 5v 4.5v 3.5v 3.3v 3v 2.8v bottom 2.5v <=60us pulse width 0.1 1 10 100 1000 1 1.5 2 2.5 3 3.5 4 v gs , gate-to-source voltage (v) i d , drain-to-source current (a) t j =150 o c tj=25 o c tj=-40 o c v ds =15v, <=60us pulse width 0.1 1 10 100 1000 0.1 1 10 100 v ds , drain-to-source voltage (v) i d , drain-to-source current (a) vgs top 10v 5v 4.5v 3.5v 3.3v 3v 2.8v bottom 2.5v 0.1 1 10 100 1000 0.1 1 10 100 v ds , drain-to-source voltage (v) i d , drain-to-source current (a) vgs top 10v 5v 4.5v 3.5v 3.3v 3v 2.8v bottom 2.5v <=60us pulse width 0.1 1 10 100 1000 1 1.5 2 2.5 3 3.5 4 v gs , gate-to-source voltage (v) i d , drain-to-source current (a) t j =150 o c tj=25 o c tj=-40 o c v ds =15v, <=60us pulse width
irf3546 60a dual integrated pow er b lock www.irf.com | ? 2013 international rectifier may 2 9 , 2013 | final 9 typical operating ch aracteristics (continue) t a = 25c , no heat sink, no air flow, 8 - layer pcb board of 3.7 (l) x 2.6 (w), unless specified otherwise. f igure 10 : q1 & q3 typical on - resistance figure 11: q1 & q3 on - resistance vs. temperature figure 12: q1 & q3 typical capacitance vs. drain - source voltage figure 13: q2 & q4 typical on - resistance figure 14: q2 & q4 on - resistance vs. temperature figure 15: q2 & q4 typical capacitance vs. drain - source voltage 10 100 1000 10000 1 10 100 v gs , drain-to-source voltage (v) typical capacitance (pf) v gs = 0v f =1mhz c iss c oss c rss 0 1 2 3 4 5 6 0 2 4 6 8 10 12 14 16 v gs , gate-to-source voltage (v) typical r ds(on) ( m ) t j =125 o c i d = 30a t j =25 o c 100 1000 10000 1 10 100 v gs , drain-to-source voltage (v) typical capacitance (pf) v gs = 0v f =1mhz c iss c oss c rss 0 2 4 6 8 10 12 0 2 4 6 8 10 12 14 16 v gs , gate-to-source voltage (v) typical r ds(on) (m) t j =125 o c i d = 27a t j =25 o c 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 -40 -20 0 20 40 60 80 100 120 140 160 t j , junction temperature ( o c) typical r ds(on) (normalized) i d = 30a v gs = 10v 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 -40 -20 0 20 40 60 80 100 120 140 160 t j , junction temperature ( o c) typical r ds(on) (normalized) i d = 27a v gs = 10v
irf3546 60a dual integrated pow er b lock www.irf.com | ? 2013 international rectifier may 2 9 , 2013 | final 10 typical operating ch aracteristics (continue) t a = 25c , no heat sink, no air flow, 4 - layer pcb board of 3.7 (l) x 2.6 ( w), unless specified otherwise. figure 16 : q1 & q3 typical on - resistance figure 17 : q1 & q3 drain - source diode characteristics figure 18: q1 & q3 typical threshold voltage vs. junction temperature figure 19 : q2 & q4 typical on - resistance figure 20 : q2 & q4 drain - source diode characteristics figure 21: q2 & q4 typical threshold voltage vs. junction temperature 0 1 2 3 4 5 6 7 8 9 10 0 20 40 60 80 100 120 140 160 i d , drain current (a ) typical r ds(on) ( m ) v gs = 4.5v v gs = 6v v gs = 7v v gs = 8v v gs = 10v 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 20 40 60 80 100 120 140 160 180 200 i d , drain current (a ) typical r ds(on) ( m ) v gs = 4.5v v gs = 6v v gs = 7v v gs = 8v v gs = 10v 0 1 10 100 1000 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 v sd , source-drain forward voltage (v) reverse drain current (a) t j = 150 o c t j = 25 o c t j = -40 o c 0 1 10 100 1000 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 v sd , source-drain forward voltage (v) reverse drain current (a) t j = 150 o c t j = 25 o c t j = -40 o c 0.0 0.5 1.0 1.5 2.0 2.5 -40 -20 0 20 40 60 80 100 120 140 160 t j , junction temperature ( o c) gate threshold voltage v gs(th) (v) i d = 10ma i d = 1ma i d = 0.25ma i d = 0.1ma i d = 0.035ma 0.0 0.5 1.0 1.5 2.0 2.5 -40 -20 0 20 40 60 80 100 120 140 160 t j , junction temperature ( o c) gate threshold voltage v gs(th) (v) i d = 100ma i d = 10ma
irf3546 60a dual integrated pow er b lock www.irf.com | ? 2013 international rectifier may 2 9 , 2013 | final 11 typical operating ch aracteristics (continue) t a = 25c , n o heat sink, no air flow, 8 - layer pcb board of 3.7 (l) x 2.6 (w), unless specified otherwise. figure 22: q1 & q3 single pulse avalanche energy figure 23: q1 & q3 maximum drain current vs. temperature figure 24 : q1 & q3 maximum safe operating area figure 25 : q2 & q4 single pulse av alanche energy figure 26: q2 & q4 maximum drain current vs. temperature figure 2 7 : q2 & q4 maximum safe operating area 0 50 100 150 200 250 300 350 400 25 50 75 100 125 150 t j , starting junction temperature ( o c) single pulse avalanche energy (mj) i d = 5a i d = 8.7a i d = 30a 0 5 10 15 20 25 30 25 50 75 100 125 150 t a , ambient temperature ( o c) i d , drain current (a) 0 0 1 10 100 1000 0.01 0.1 1 10 100 v ds , drain-to-source voltage (v ) i d , drain-to-source current (a) t a = 25 o c t j = 150 o c single pulse operation in this area limited by r ds (on) dc 10ms 1ms 100us 0 500 1000 1500 2000 2500 3000 25 50 75 100 125 150 t j , starting junction temperature ( o c) single pulse avalanche energy (mj) i d = 6.5a i d = 11a i d = 30a 0 5 10 15 20 25 30 35 40 45 25 50 75 100 125 150 t a , ambient temperature ( o c) i d , drain current (a) 0 0 1 10 100 1000 0.01 0.1 1 10 100 v ds , drain-to-source voltage (v ) i d , drain-to-source current (a) t a = 25 o c t j = 150 o c single pulse operation in this area limited by r ds (on) dc 10ms 1ms 100us
irf3546 60a dual integrated pow er b lock www.irf.com | ? 2013 international rectifier may 2 9 , 2013 | final 12 general descript ion the ir f3546 contains two pairs of integrated high and low side n - channel mosfets . it is suitable for high switching frequency operation . the ir f3546 can be driven as two independent power stages or as one power stage in a two - phase interleaved conver ter . application informat ion figure 3 shows a typical two phase, high density application circuit for the irf3546. supply d ecoupling c apacitor at least two 10uf 1206 ceramic capacitors and one 0.1uf 0402 ceramic capacitor are recommended for decoupling t he vin to pgnd connection of each mosfet pair . the 0.1uf 0402 capacitor should be on the same side of the pcb as the ir f 3546 and next to the vin and pgnd pins. adding additional capacitance and use of capacitors with lower esr and mounted with low inductan ce routing will improve efficiency and reduce overall system noise, especially in high current applications . pcb layout considera tion pcb layout and design is important to driver performance in voltage regulator circuits due to the high current slew rate (di/dt) during mosfet switching. locate all power components in each phase as close to each other as practically possible in order to minimize parasitics and losses, allowing for reasonable airflow. input supply decoupling capacitors should be physically located close to their respective pins. high current paths like the gate driver traces should be as wide and short as practically possible. gatel1 and gatel2 interconnect trace inductances should be minimized to prevent cdv/dt turn - on of the low side mosfe t. the ground connection should be as close as possible to the low - side mosfet source. use of a copper plane under and around the device and thermal vias to connect to buried copper layers improves the thermal performance substantially.
irf3546 60a dual integrated pow er b lock www.irf.com | ? 2013 international rectifier may 2 9 , 2013 | final 13 metal and component placement ? lead land width should be equal to nominal part lead width. the minimum lead to lead spacing should be 0.2mm to prevent shorting. ? lead land length should be equal to maximum part lead length +0.15 - 0.3 mm outboard extensio n and 0 to + 0.05mm inboard extension. the outboard extension ensures a large and visible toe fillet, and the inboard extension will accommodate any part misalignment and ensure a fillet. ? center pad land length and width should be equal to maximum part pad length and width. ? only 0.30mm diameter via shall be placed in the area of the power pad lands and connected to power planes to mini mize the noise effect and to improve thermal performance. figure 2 8 : metal and compon ent placement
irf3546 60a dual integrated pow er b lock www.irf.com | ? 2013 international rectifier may 2 9 , 2013 | final 14 solder resist ? the solder resist should be pulled away from the metal lead lands by a minimum of 0.06mm. the solder resist miss - alignment is a maximum of 0.05mm and it is recommended that the low power signal lead lands are all non solder mask defined (nsmd). therefore pulling the s/r 0.06mm will always ensure nsmd pads. ? the minimum solder resist width is 0.13mm typical. ? at the inside corner of the solder resist where the lead land groups meet, it is recommended to provide a fillet so a solder resist width of 0.17mm remains. ? the power land pads vin 1 , vin2, pgnd, sw1 and sw 2 should be solder mask defined (smd). ? ensure that the solder resist in - between the lead lands and the pad land is 0.15mm due to the high aspect ratio of the sold er resist strip separating the lead lands from the pad land. figure 2 9 : solder resist
irf3546 60a dual integrated pow er b lock www.irf.com | ? 2013 international rectifier may 2 9 , 2013 | final 15 stencil design ? the stencil apertures for the lead lands should be approximately 65% to 75% of the area of the lead lands depending on s tencil thickness. reducing the amount of solder deposited will minimize the occurrence of lead shorts. since for 0.5mm pitch devices the leads are only 0.25mm wide, the stencil apertures should not be made narrower; openings in stencils < 0.25mm wide are d ifficult to maintain repeatable solder release. ? the low power signal stencil lead land apertures should therefore be shortened in length to keep area ratio of 65% to 75% while centered on lead land. ? the power pads vin 1, vin2 , pgnd , sw1 and sw 2 , land pad apertures should be approximately 65% to 75% area of solder on the center pad. if too much solder is deposited on the center pad the part will float and the lead lands will be open. solder paste on large pads is broken down into small sections with a minim um gap of 0.2mm between allowing for out - gassing during solder reflow. ? the maximum length and width of the land pad stencil aperture should be equal to the solder resist opening minus an annular 0.2mm pull back to decrease the incidence of shorting the cen ter land to the lead lands when the part is pushed into the solder paste. figure 30 : stencil design
irf3546 60a dual integrated pow er b lock www.irf.com | ? 2013 international rectifier may 2 9 , 2013 | final 16 marking information figure 31 : pqfn 6mm x 8mm f3546 m ? yww ? xxxx / / marking code(?) lot code assembly site(?)/ date(yww)
irf3546 60a dual integrated pow er b lock www.irf.com | ? 2013 international rectifier may 2 9 , 2013 | final 17 package information figure 32 : pqfn 6mm x 8mm
ir f3546 60a dual integrated powirblock tm www.irf.com | ? 2013 internat ional rectifier may 2 9 , 2013 | final 18 data and specifications subject to change without notice. this product will be designed and qualified for the consumer market. qualification standards can be found on irs web site. ir w orld headquarters: 233 kansas st., el segundo, california 90245, usa tel: (310) 252 - 7105 tac fax: (310) 252 - 7903 visit us at www.irf.com for sales contact information . www.irf.com

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